 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| MCP3002 2.7V Dual Channel 10-Bit A/D Converter with SPITM Serial Interface FEATURES * * * * * * * * * * 10-bit resolution 1 LSB max DNL 1 LSB max INL Analog inputs programmable as single-ended or pseudo-differential pairs On-chip sample and hold SPI(R) serial interface (modes 0,0 and 1,1) Single supply operation: 2.7V - 5.5V 200ksps max sampling rate at VDD = 5V 75ksps max sampling rate at VDD = 2.7V Low power CMOS technology - 5nA typical standby current, 2A max - 550A max. active current at 5V Industrial temp range: -40C to +85C 8-pin PDIP SOIC and TSSOP packages PACKAGE TYPES PDIP CS/SHDN CH0 CH1 VSS 1 2 3 4 8 7 6 5 VDD/VREF CLK DOUT DIN MCP3002 SOIC, TSSOP CS/SHDN CH0 CH1 VSS * * 1 2 3 4 8 7 6 5 MCP3002 VDD/VREF CLK DOUT DIN APPLICATIONS * * * * Sensor Interface Process Control Data Acquisition Battery Operated Systems FUNCTIONAL BLOCK DIAGRAM VDD VSS DESCRIPTION The Microchip Technology Inc. MCP3002 is a successive approximation 10-bit Analog-to-Digital (A/D) Converter with on-board sample and hold circuitry. The MCP3002 is programmable to provide a single pseudo-differential input pair or dual single-ended inputs. Differential Nonlinearity (DNL) and Integral Nonlinearity (INL) are both specified at 1 LSB. Communication with the device is done using a simple serial interface compatible with the SPI protocol. The device is capable of conversion rates of up to 200ksps at 5V and 75ksps at 2.7V. The MCP3002 device operates over a broad voltage range (2.7V - 5.5V). Low current design permits operation with a typical standby current of 5nA and a typical active current of 375A. The MCP3002 is offered in 8-pin PDIP, TSSOP and 150mil SOIC packages. CH0 CH1 Input Channel Mux DAC Comparator Sample and Hold Control Logic 10-Bit SAR Shift Register CS/SHDN DIN CLK DOUT SPI is a trademark of Motorola Inc. 2000 Microchip Technology Inc. Preliminary DS21294A-page 1 MCP3002 1.0 1.1 ELECTRICAL CHARACTERISTICS Maximum Ratings* PIN FUNCTION TABLE NAME VDD/VREF CH0 CH1 CLK DIN DOUT CS/SHDN FUNCTION +2.7V To 5.5V Power Supply and Reference Voltage Input Channel 0 Analog Input Channel 1 Analog Input Serial Clock Serial Data In Serial Data Out Chip Select/Shutdown Input VDD.........................................................................7.0V All inputs and outputs w.r.t. VSS ...... -0.6V to VDD +0.6V Storage temperature ..........................-65C to +150C Ambient temp. with power applied......-65C to +125C Soldering temperature of leads (10 seconds) .. +300C ESD protection on all pins ................................... > 4kV *Notice: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS All parameters apply at VDD = 5V, TAMB = -40C to +85C, fSAMPLE = 200ksps and fCLK = 16*fSAMPLE unless otherwise noted. Typical values apply for VDD = 5V, TAMB =25C unless otherwise noted. PARAMETER Conversion Rate Conversion Time Analog Input Sample Time Throughput Rate DC Accuracy Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error Dynamic Performance Total Harmonic Distortion Signal to Noise and Distortion (SINAD) Spurious Free Dynamic Range Analog Inputs Input Voltage Range for CH0 or CH1 in Single-Ended Mode Input Voltage Range for IN+ In pseudo-differential Mode Input Voltage Range for IN- In pseudo-differential Mode Leakage Current Switch Resistance Sample Capacitor RSS CSAMPLE VSS INVSS-100 0.001 1K 20 VDD VDD+INVSS+100 1 mV A pF See Figure 4-1 See Figure 4-1 V -76 61 78 dB dB dB VIN = 0.1V to 4.9V@1kHz VIN = 0.1V to 4.9V@1kHz VIN = 0.1V to 4.9V@1kHz INL DNL 10 0.5 0.25 1 1 1.5 1 bits LSB LSB LSB LSB No missing codes over temperature tCONV tSAMPLE fSAMPLE 1.5 200 75 10 clock cycles clock cycles ksps ksps VDD = 5V VDD = 2.7V SYMBOL MIN. TYP. MAX. UNITS CONDITIONS DS21294A-page 2 Preliminary 2000 Microchip Technology Inc. MCP3002 ELECTRICAL CHARACTERISTICS (CONTINUED) All parameters apply at VDD = 5V, TAMB = -40C to +85C, fSAMPLE = 200ksps and fCLK = 16*fSAMPLE unless otherwise noted. Typical values apply for VDD = 5V, TAMB =25C unless otherwise noted. PARAMETER Digital Input/Output Data Coding Format High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Input Leakage Current Output Leakage Current Pin Capacitance (All Inputs/Outputs) Timing Parameters Clock Frequency Clock High Time Clock Low Time CS Fall To First Rising CLK Edge Data Input Setup Time Data Input Hold Time CLK Fall To Output Data Valid CLK Fall To Output Enable CS Rise To Output Disable CS Disable Time DOUT Rise Time DOUT Fall Time Power Requirements Operating Voltage Operating Current Standby Current VDD IDD IDDS 2.7 -- -- 525 300 0.005 5.5 650 2 V A A VDD = 5.0V, DOUT Unloaded VDD = 2.7V, DOUT Unloaded CS = VDD = 5.0V fCLK tHI tLO tSUCS tSU tHD tDO tEN tDIS tCSH tR tF 310 100 100 140 140 100 50 50 125 200 125 200 100 3.2 1.2 MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns See Test Circuits,Figure 1-2 Note 1 See Test Circuits,Figure 1-2 Note 1 VDD = 5V, See Figure 1-2 VDD = 2.7, See Figure 1-2 VDD = 5V, See Figure 1-2 VDD = 2.7, See Figure 1-2 See Test Circuits,Figure 1-2 Note 1 VDD = 5V (Note 2) VDD = 2.7V (Note 2) VIH VIL VOH VOL ILI ILO CIN, COUT -- 4.1 -- -10 -10 -- Straight Binary 0.7 VDD -- 0.3 VDD -- 0.4 10 10 10 V V V V A A pF IOH = -1mA, VDD = 4.5V IOL = 1mA, VDD = 4.5V VIN = VSS or VDD VOUT = VSS or VDD VDD = 5.0V (Note 1) TAMB = 25C, f = 1 MHz SYMBOL MIN. TYP. MAX. UNITS CONDITIONS Note 1: This parameter is guaranteed by characterization and not 100% tested. Note 2: The sample cap will eventually lose charge, especially at elevated temperatures, therefore fCLK 10kHz for temperatures at or above 70C. . 2000 Microchip Technology Inc. Preliminary DS21294A-page 3 MCP3002 tCSH CS tSUCS tHI CLK tSU DIN tHD tLO MSB IN tEN tDO NULL BIT MSB OUT tR tF LSB tDIS DOUT FIGURE 1-1: Serial Timing. Test Point 1.4V 3K Test Point DOUT CL = 30pF 30pF VSS 3K VDD VDD/2 tDIS Waveform 2 tEN Waveform tDIS Waveform 1 DOUT Voltage Waveforms for tR, tF DOUT VOH VOL Voltage Waveforms for tEN CS 1 CLK DOUT 2 3 4 B9 tR tF tEN Voltage Waveforms for tDO Voltage Waveforms for tDIS CS VIH 90% CLK tDO DOUT DOUT Waveform 1* tDIS DOUT Waveform 2 * 10% Waveform 1 is for an output with internal conditions such that the output is high, unless disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is low, unless disabled by the output control. FIGURE 1-2: Test Circuits. DS21294A-page 4 Preliminary 2000 Microchip Technology Inc. MCP3002 2.0 TYPICAL PERFORMANCE CHARACTERISTICS Note: Unless otherwise indicated, VDD = 5V, fSAMPLE = 200ksps, fCLK = 16* fSAMPLE,TA = 25C 0.6 0.4 0.6 VDD = 2.7V 0.4 INL (LSB) INL (LSB) 0.2 0.0 -0.2 -0.4 -0.6 0 25 Positive INL 0.2 0.0 -0.2 -0.4 -0.6 Positive INL Negative INL Negative INL 50 75 100 125 150 175 200 225 250 0 25 50 75 100 Sample Rate (ksps) Sample Rate (ksps) FIGURE 2-1: Rate. Integral Nonlinearity (INL) vs. Sample FIGURE 2-4: Integral Nonlinearity (INL) vs. Sample Rate (VDD = 2.7V). 1.0 0.8 0.6 0.4 VDD = 5V fSAMPLE = 200ksps 1.0 0.8 0.6 0.4 VDD = 2.7V fSAMPLE = 75ksps INL (LSB) INL (LSB) 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 0 128 256 384 512 640 768 896 1024 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 0 128 256 384 512 640 768 896 1024 Digital Code Digital Code FIGURE 2-2: Integral Nonlinearity (INL) vs. Code. FIGURE 2-5: (VDD = 2.7V). Integral Nonlinearity (INL) vs. Code 0.5 0.4 0.3 0.2 Positive INL 0.5 0.4 0.3 0.2 0.1 0.0 -0.1 -0.2 -0.3 -0.4 -0.5 Negative INL VDD = 2.7V fSAMPLE = 75ksps Positive INL INL (LSB) 0.1 0.0 -0.1 -0.2 -0.3 -0.4 -0.5 -50 -25 0 25 50 75 100 Negative INL INL (LSB) -50 -25 0 25 50 75 100 Temperature (C) Temperature (C) FIGURE 2-3: Temperature. Integral Nonlinearity (INL) vs. FIGURE 2-6: Integral Nonlinearity Temperature (VDD = 2.7V). (INL) vs. 2000 Microchip Technology Inc. Preliminary DS21294A-page 5 MCP3002 Note: Unless otherwise indicated, VDD = 5V, fSAMPLE = 200ksps, fCLK = 16* fSAMPLE,TA = 25C 1.0 0.8 0.6 0.4 Positive INL 0.8 0.6 0.4 Positive DNL DNL (LSB) INL(LSB) 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Negative INL 0.2 0.0 -0.2 Negative DNL -0.4 -0.6 -0.8 2.5 3.0 3.5 4.0 4.5 5.0 5.5 All points taken at fSAMPLE = 200ksps except VDD = 2.7V, fSAMPLE = 75ksps All points taken at fSAMPLE = 200ksps except VDD = 2.7V, fSAMPLE = 75ksps VDD (V) VDD(V) FIGURE 2-7: Integral Nonlinearity (INL) vs. VDD. FIGURE 2-10: Differential Nonlinearity (DNL) vs. VDD. 0.6 0.4 0.6 VDD = 2.7V 0.4 DNL (LSB) DNL (LSB) 0.2 0.0 -0.2 -0.4 -0.6 0 25 Positive DNL 0.2 0.0 -0.2 -0.4 -0.6 Positive DNL Negative DNL Negative DNL 50 75 100 125 150 175 200 225 250 0 25 50 75 100 Sample Rate (ksps) Sample Rate (ksps) FIGURE 2-8: Differential Sample Rate. Nonlinearity (DNL) vs. FIGURE 2-11: Differential Nonlinearity Sample Rate (VDD = 2.7V). (DNL) vs. 1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 0 128 256 384 512 640 768 896 1024 VDD = 5V fSAMPLE = 200 ksps 1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 0 128 256 384 512 640 768 896 1024 VDD = 2.7V fSAMPLE = 75 ksps DNL (LSB) DNL (LSB) Digital Code Digital Code FIGURE 2-9: Differential Nonlinearity Code (Representative Part). (DNL) vs. FIGURE 2-12: Differential Nonlinearity Code (Representative Part, VDD = 2.7V). (DNL) vs. DS21294A-page 6 Preliminary 2000 Microchip Technology Inc. MCP3002 Note: Unless otherwise indicated, VDD = 5V, fSAMPLE = 200ksps, fCLK = 16* fSAMPLE,TA = 25C 0.4 0.3 0.2 Positive DNL 0.4 0.3 0.2 VDD = 2.7V fSAMPLE = 75ksps Positive DNL DNL (LSB) DNL (LSB) 0.1 0.0 -0.1 -0.2 -0.3 -0.4 -50 -25 0 25 50 75 100 Negative DNL 0.1 0.0 -0.1 -0.2 -0.3 -0.4 -50 -25 0 25 50 75 100 Negative DNL Temperature (C) Temperature (C) FIGURE 2-13: Differential Temperature. Nonlinearity (DNL) vs. FIGURE 2-16: Differential Temperature (VDD = 2.7V). Nonlinearity (DNL) vs. 1.0 0.8 All points taken at fSAMPLE = 200ksps except VDD = 2.7V, fSAMPLE = 75ksps 1.0 All points taken at fSAMPLE = 200ksps except 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Offset Error (LSB) Gain Error (LSB) 0.6 0.8 0.6 0.4 0.2 0.0 2.5 VDD = 2.7V, fSAMPLE = 75ksps 3.0 3.5 4.0 4.5 5.0 5.5 VDD(V) V DD (V) FIGURE 2-14: Gain Error vs. VDD. FIGURE 2-17: Offset Error vs. VDD. 0.0 -0.1 -0.2 -0.3 VDD = 5V VDD = 2.7V fSAMPLE = 75ksps 0.8 0.7 Offset Error (LSB) Gain Error (LSB) 0.6 0.5 0.4 0.3 0.2 0.1 VDD = 2.7V fSAMPLE = 75ksps VDD = 5V fSAMPLE = 200ksps -0.4 -0.5 -50 fSAMPLE = 200ksps 0.0 -25 0 25 50 75 100 -50 -25 0 25 50 75 100 Temperature (C) Temperature (C) FIGURE 2-15: Gain Error vs. Temperature. FIGURE 2-18: Offset Error vs. Temperature. 2000 Microchip Technology Inc. Preliminary DS21294A-page 7 MCP3002 Note: Unless otherwise indicated, VDD = 5V, fSAMPLE = 200ksps, fCLK = 16* fSAMPLE,TA = 25C 80 70 60 50 40 30 20 10 0 1 10 100 VDD = 2.7V fSAMPLE = 75ksps VDD = 5V fSAMPLE = 200ksps 80 VDD = 5V 70 60 fSAMPLE = 200ksps SINAD (dB) SNR (dB) 50 VDD = 2.7V 40 30 20 10 0 1 fSAMPLE = 75ksps 10 100 Input Frequency (kHz) Input Frequency (kHz) FIGURE 2-19: Signal to Noise Ratio (SNR) vs. Input Frequency. FIGURE 2-22: Signal to Noise (SINAD) vs. Input Frequency. and Distortion 0 -10 -20 80 70 VDD = 5V fSAMPLE = 200ksps SINAD (dB) -30 VDD = 2.7V fSAMPLE = 75ksps 60 50 40 30 20 VDD = 5V fSAMPLE = 200ksps THD (dB) -40 -50 -60 -70 -80 -90 -100 1 10 0 100 VDD = 2.7V fSAMPLE = 75ksps 10 -40 -35 -30 -25 -20 -15 -10 -5 0 Input Frequency (kHz) Input Signal Level (dB) FIGURE 2-20: Total Harmonic Distortion (THD) vs. Input Frequency . FIGURE 2-23: Signal to Noise (SINAD) vs. Signal Level. and Distortion 10.0 9.9 10.0 9.5 9.8 9.7 9.6 9.5 9.4 2.5 3.0 3.5 4.0 4.5 5.0 5.5 All points at fSAMPLE = 200ksps except VDD = 2.7V, fSAMPLE = 75ksps ENOB (rms) ENOB 9.0 VDD = 2.7V fSAMPLE = 75ksps 8.5 VDD = 5V fSAMPLE = 200ksps 8.0 1 10 100 VDD (V) Input Frequency (kHz) FIGURE 2-21: Effective number of bits (ENOB) vs. VDD. FIGURE 2-24: Effective Number of Bits (ENOB) vs. Input Frequency. DS21294A-page 8 Preliminary 2000 Microchip Technology Inc. MCP3002 Note: Unless otherwise indicated, VDD = 5V, fSAMPLE = 200ksps, fCLK = 16* fSAMPLE,TA = 25C 100 90 80 70 VDD = 2.7V fSAMPLE = 75ksps VDD = 5V fSAMPLE = 200ksps 600 500 400 SFDR (dB) 50 40 30 20 10 0 1 IDD (A) 60 300 200 100 0 All points at fCLK = 3.2Mhz except at VDD = 2.5V, fCLK = 1.2Mhz 10 100 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Input Frequency (kHz) VDD (V) FIGURE 2-25: Spurious Free (SFDR) vs. Input Frequency. Dynamic Range FIGURE 2-28: IDD vs. VDD. 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 0 20000 40000 VDD = 5V fSAMPLE = 200ksps fINPUT = 10.976kHz 4096 points 60000 80000 100000 600 550 500 450 400 350 300 250 200 150 100 50 0 10 Amplitude (dB) IDD (A) VDD = 5V VDD = 2.7V 100 1000 10000 Frequency (Hz) Clock Frequency (kHz) FIGURE 2-26: Frequency Spectrum of 10kHz input (Representative Part). FIGURE 2-29: IDD vs. Clock Frequency. 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 0 VDD = 2.7V fSAMPLE = 75ksps fINPUT = 1.00708kHz 4096 points 600 500 400 300 200 100 0 VDD = 2.7V fCLK = 1.2Mhz VDD = 5V fCLK = 3.2Mhz Amplitude (dB) 5000 10000 15000 20000 25000 30000 35000 IDD (A) -50 -25 0 25 50 75 100 Frequency (Hz) Temperature (C) FIGURE 2-27: Frequency Spectrum of 1kHz input (Representative Part, VDD = 2.7V). FIGURE 2-30: IDDvs. Temperature. 2000 Microchip Technology Inc. Preliminary DS21294A-page 9 MCP3002 Note: Unless otherwise indicated, VDD = 5V, fSAMPLE = 200ksps, fCLK = 16* fSAMPLE,TA = 25C 70 2.0 Analog Input Leakage (nA) CS = VDD 60 50 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 -50 VDD = 5V IDDS (pA) 40 30 20 10 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 -25 0 25 50 75 100 Temperature (C) VDD (V) FIGURE 2-31: IDDS vs. VDD. FIGURE 2-33: Analog Input leakage current vs. Temperature. 100.00 VDD = CS = 5V 10.00 IDDS (nA) 1.00 0.10 0.01 -50 -25 0 25 50 75 100 Temperature (C) FIGURE 2-32: IDDS vs. Temperature. DS21294A-page 10 Preliminary 2000 Microchip Technology Inc. MCP3002 3.0 3.1 PIN DESCRIPTIONS CH0/CH1 4.1 Analog Inputs Analog inputs for channels 0 and 1 respectively. These channels can programmed to be used as two independent channels in single ended-mode or as a single pseudo-differential input where one channel is IN+ and one channel is IN-. See Section 5.0 for information on programming the channel configuration. 3.2 CS/SHDN(Chip Select/Shutdown) The CS/SHDN pin is used to initiate communication with the device when pulled low and will end a conversion and put the device in low power standby when pulled high. The CS/SHDN pin must be pulled high between conversions. The MCP3002 device offers the choice of using the analog input channels configured as two single-ended inputs that are referenced to VSS or a single pseudo-differential input. The configuration setup is done as part of the serial command before each conversion begins. When used in the psuedo-differential mode, CH0 and CH1 are programmed as the IN+ and IN- inputs as part of the command string transmitted to the device. The IN+ input can range from IN- to the reference voltage, VDD. The IN- input is limited to 100mV from the VSS rail. The IN- input can be used to cancel small signal common-mode noise which is present on both the IN+ and IN- inputs. For the A/D Converter to meet specification, the charge holding capacitor (CSAMPLE) must be given enough time to acquire a 10-bit accurate voltage level during the 1.5 clock cycle sampling period. The analog input model is shown in Figure 4-1. In this diagram, it is shown that the source impedance (RS) adds to the internal sampling switch (RSS) impedance, directly affecting the time that is required to charge the capacitor, CSAMPLE. Consequently, larger source impedances increase the offset, gain, and integral linearity errors of the conversion. Ideally, the impedance of the signal source should be near zero. This is achievable with an operational amplifier such as the MCP601 which has a closed loop output impedance of tens of ohms. The adverse affects of higher source impedances are shown in Figure 4-2. When operating in the pseudo-differential mode, if the voltage level of IN+ is equal to or less than IN-, the resultant code will be 000h. If the voltage at IN+ is equal to or greater than {[VDD + (IN-)] - 1 LSB}, then the output code will be 3FFh. If the voltage level at IN- is more than 1 LSB below VSS, then the voltage level at the IN+ input will have to go below VSS to see the 000h output code. Conversely, if IN- is more than 1 LSB above VSS, then the 3FFh code will not be seen unless the IN+ input level goes above VDD level. If the voltage at IN+ is equal to or greater than {[VDD + (IN-)] - 1 LSB}, then the output code will be 3FFh. 3.3 CLK (Serial Clock) The SPI clock pin is used to initiate a conversion and to clock out each bit of the conversion as it takes place. See Section 6.2 for constraints on clock speed. 3.4 DIN (Serial Data Input) The SPI port serial data input pin is used to clock in input channel configuration data. 3.5 DOUT (Serial Data output) The SPI serial data output pin is used to shift out the results of the A/D conversion. Data will always change on the falling edge of each clock as the conversion takes place. 4.0 DEVICE OPERATION The MCP3002 A/D converter employs a conventional SAR architecture. With this architecture, a sample is acquired on an internal sample/hold capacitor for 1.5 clock cycles starting on the second rising edge of the serial clock after the start bit has been received. Following this sample time, the input switch of the converter opens and the device uses the collected charge on the internal sample and hold capacitor to produce a serial 10-bit digital output code. Conversion rates of 200ksps are possible on the MCP3002. See Section 6.2 for information on minimum clock rates. Communication with the device is done using a 3-wire SPI compatible interface. 2000 Microchip Technology Inc. Preliminary DS21294A-page 11 MCP3002 4.2 Digital Output Code The digital output code produced by an A/D Converter is a function of the input signal and the reference voltage. For the MCP3002, VDD is used as the reference voltage. LSB Size = VREF 1024 As the VDD level is reduced, the LSB size is reduced accordingly. The theoretical digital output code produced by the A/D Converter is shown below. Digital Output Code = 1024 * VIN VDD where: VIN = analog input voltage VDD = supply voltage VDD VT = 0.6V Sampling Switch SS RSS = 1k CSAMPLE = DAC capacitance = 20 pF VSS RS CHx CPIN 7pF VA VT = 0.6V ILEAKAGE 1nA Legend VA = signal source RS = source impedance CHx = input channel pad CPIN = input pin capacitance VT = threshold voltage ILEAKAGE = leakage current at the pin due to various junctions SS = sampling switch RSS = sampling switch resistor CSAMPLE = sample/hold capacitance FIGURE 4-1: Analog Input Model. 4.0 Clock Frequency (Mhz) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 100 1000 VDD = 2.7V fSAMPLE = 75ksps VDD = 5V fSAMPLE = 200ksps 10000 Input Resistance (Ohms) FIGURE 4-2: Maximum Clock Frequency vs. Input resistance (RS) to maintain less than a 0.1LSB deviation in INL from nominal conditions. DS21294A-page 12 Preliminary 2000 Microchip Technology Inc. MCP3002 5.0 5.1 SERIAL COMMUNICATIONS Overview Communication with the MCP3002 is done using a standard SPI-compatible serial interface. Initiating communication with the device is done by bringing the CS line low. See Figure 5-1. If the device was powered up with the CS pin low, it must be brought high and back low to initiate communication. The first clock received with CS low and DIN high will constitute a start bit. The SGL/DIFF bit and the ODD/SIGN bit follow the start bit and are used to select the input channel configuration. The SGL/DIFF is used to select single ended or psuedo-differential mode. The ODD/SIGN bit selects which channel is used in single ended mode, and is used to determine polarity in psuedo-differential mode. Following the ODD/SIGN bit, the MSBF bit is transmitted to and is used to enable the LSB first format for the device. If the MSBF bit is low, then the data will come from the device in MSB first format and any further clocks with CS low, will cause the device to output zeros. If the MSBF bit is high, then the device will output the converted word LSB first after the word has been transmitted in the MSB first format. Table 5-1 shows the configuration bits for the MCP3002. The device will begin to sample the analog input on the second rising edge of the clock, after the start bit has been received. The sample period will end on the falling edge of the third clock following the start bit. On the falling edge of the clock for the MSBF bit, the device will output a low null bit. The next sequential 10 clocks will output the result of the conversion with MSB first as shown in Figure 5-1. Data is always output from the device on the falling edge of the clock. If all 10 data bits have been transmitted and the device continues to receive clocks while the CS is held low (and the MSBF bit is high), the device will output the conversion result LSB first as shown in Figure 5-2. If more clocks are provided to the device while CS is still low (after the LSB first data has been transmitted), the device will clock out zeros indefinitely. If necessary, it is possible to bring CS low and clock in leading zeros on the DIN line before the start bit. This is often done when dealing with microcontroller-based SPI ports that must send 8 bits at a time. Refer to Section 6.1 for more details on using the MCP3002 devices with hardware SPI ports. If it is desired, the CS can be raised to end the conversion period at any time during the transmission. Faster conversion rates can be obtained by using this technique if not all the bits are captured before starting a new cycle. Some system designers use this method by capturing only the highest order 8 bits and `throwing away' the lower 2 bits. CONFIG BITS SGL/ DIFF SINGLE ENDED MODE PSEUDODIFFERENTIAL MODE 1 1 0 0 ODD/ SIGN 0 1 0 1 IN+ INCHANNEL SELECTION 0 + + ININ+ 1 GND TABLE 5-1: Configuration Bits for the MCP3002. 2000 Microchip Technology Inc. Preliminary DS21294A-page 13 MCP3002 tCYC tCSH CS tSUCS CLK tCYC DIN Start SGL/ ODD/ MS DIFF SIGN BF Don't Care Start SGL/ ODD/ DIFF SIGN DOUT HI-Z Null Bit HI-Z B9 B8 B7 B6 B5 B4 B3 B2 B1 B0* tSAMPLE tCONV tDATA** * After completing the data transfer, if further clocks are applied with CS low, the A/D Converter will output zeros indefinitely. See Figure 5-2 for details on obtaining LSB first data. ** tDATA: during this time, the bias current and the comparator powers down while the reference input becomes a high impedance node. FIGURE 5-1: Communication with the MCP3002 using MSB first format only. tCYC tCSH CS tSUCS CLK Power Down MSBF Start ODD/ SIGN SGL/ DIFF DIN Don't Care DOUT HI-Z Null * B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 Bit HI-Z tSAMPLE (MSB) tCONV tDATA ** * After completing the data transfer, if further clocks are applied with CS low, the A/D Converter will output zeros indefinitely. ** tDATA: During this time, the bias circuit and the comparator powers down while the reference input becomes a high impedance node, leaving the CLK running to clock out LSB first data or zeroes. FIGURE 5-2: Communication with MCP3002 using LSB first format. DS21294A-page 14 Preliminary 2000 Microchip Technology Inc. MCP3002 6.0 6.1 APPLICATIONS INFORMATION Using the MCP3002 with Microcontroller (MCU) SPI Ports be interfaced to a MCU with a hardware SPI port. Figure 6-1 depicts the operation shown in SPI Mode 0,0, which requires that the SCLK from the MCU idles in the `low' state, while Figure 6-2 shows the similar case of SPI Mode 1,1 where the clock idles in the `high' state. As shown in Figure 6-1, the first byte transmitted to the A/D Converter contains one leading zero before the start bit. Arranging the leading zero this way produces the output 10 bits to fall in positions easily manipulated by the MCU. When the first 8 bits are transmitted to the device, the MSB data bit is clocked out of the A/D Converter on the falling edge of clock number 6. After the second eight clocks have been sent to the device, the receive register will contain the lowest order eight bits of the conversion results. Easier manipulation of the converted data can be obtained by using this method. With most microcontroller SPI ports, it is required to send groups of eight bits. It is also required that the microcontroller SPI port be configured to clock out data on the falling edge of clock and latch data in on the rising edge. Depending on how communication routines are used, it is very possible that the number of clocks required for communication will not be a multiple of eight. Therefore, it may be necessary for the MCU to send more clocks than are actually required. This is usually done by sending `leading zeros' before the start bit, which are ignored by the device. As an example, Figure 6-1 and Figure 6-2 show how the MCP3002 can CS MCU latches data from A/D Converter on rising edges of SCLK SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Data is clocked out of A/D Converter on falling edges DIN SGL/ Start DIFF MSBF ODD/ SIGN Don't Care DOUT Start Bit MCU Transmitted Data (Aligned with falling edge of clock) MCU Received Data (Aligned with rising edge of clock) X X 1 NULL B9 BIT B8 B7 B6 B5 B4 B3 B2 B1 B0 SGL/ ODD/ MSBF DIFF SIGN X X X X X X X X X X X X X X X 0 (Null) B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 X = Don't Care Bits Data stored into MCU receive register after transmission of first 8 bits Data stored into MCU receive register after transmission of second 8 bits FIGURE 6-1: SPI Communication with the MCP3002 using 8-bit segments (Mode 0,0: SCLK idles low). CS MCU latches data from A/D Converter on rising edges of SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Data is clocked out of A/D Converter on falling edges SCLK DIN MSBF ODD/ SIGN SGL/ DIFF Start Don't Care DOUT HI-Z NULL BIT B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 MCU Transmitted Data (Aligned with falling edge of clock) MCU Received Data (Aligned with rising edge of clock) Start Bit X 1 SGL/ ODD/ MSBF DIFF SIGN X X X X X X X X X X X X X X X X 0 (Null) B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 X = Don't Care Bits Data stored into MCU receive register after transmission of first 8 bits Data stored into MCU receive register after transmission of second 8 bits FIGURE 6-2: SPI Communication with the MCP3002 using 8-bit segments (Mode 1,1: SCLK idles high). 2000 Microchip Technology Inc. Preliminary DS21294A-page 15 MCP3002 6.2 Maintaining Minimum Clock Speed 6.4 Layout Considerations When the MCP3002 initiates the sample period, charge is stored on the sample capacitor. When the sample period is complete, the device converts one bit for each clock that is received. It is important for the user to note that a slow clock rate will allow charge to bleed off the sample cap while the conversion is taking place. At 85C (worst case condition), the part will maintain proper charge on the sample cap for 700s at VDD = 2.7V and 1.5ms at VDD = 5V. This means that at VDD = 2.7V, the time it takes to transmit the 1.5 clocks for the sample period and the 10 clocks for the actual conversion must not exceed 700s. Failure to meet this criteria may induce linearity errors into the conversion outside the rated specifications. When laying out a printed circuit board for use with analog components, care should be taken to reduce noise wherever possible. A bypass capacitor should always be used with this device and should be placed as close as possible to the device pin. A bypass capacitor value of 1F is recommended. Digital and analog traces should be separated as much as possible on the board and no traces should run underneath the device or the bypass capacitor. Extra precautions should be taken to keep traces with high frequency signals (such as clock lines) as far as possible from analog traces. Use of an analog ground plane is recommended in order to keep the ground potential the same for all devices on the board. Providing VDD connections to devices in a "star" configuration can also reduce noise by eliminating current return paths and associated errors. See Figure 6-4. For more information on layout tips when using A/D converters, refer to AN-688 "Layout Tips for 12-Bit A/D Converter Applications". VDD Connection 6.3 Buffering/Filtering the Analog Inputs If the signal source for the A/D Converter is not a low impedance source, it will have to be buffered or inaccurate conversion results may occur. It is also recommended that a filter be used to eliminate any signals that may be aliased back in to the conversion results. This is illustrated in Figure 6-3 below where an op amp is used to drive, filter, and gain the analog input of the MCP3002. This amplifier provides a low impedance output for the converter input and a low pass filter, which eliminates unwanted high frequency noise. Low pass (anti-aliasing) filters can be designed using Microchip's interactive FilterLabTM software. FilterLab will calculate capacitor and resistors values, as well as, determine the number of poles that are required for the application. For more information on filtering signals, see the application note AN699 "Anti-Aliasing Analog Filters for Data Acquisition Systems." VDD 10uF Device 4 Device 1 Device 3 Device 2 1F IN+ MCP3002 R1 C1 R2 C2 R3 R4 MCP601 IN- FIGURE 6-4: VDD traces arranged in a `Star' configuration in order to reduce errors caused by current return paths. VIN + - FIGURE 6-3: Typical (2 pole Active Filter). Anti-Aliasing Filter Circuit DS21294A-page 16 Preliminary 2000 Microchip Technology Inc. MCP3002 MCP3002 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. MCP3002 - X /X Package: P = PDIP (8 lead) SN = SOIC (150 mil Body), 8 lead ST = TSSOP, 8 lead I = -40C to +85C Temperature Range: Device: MCP3002 = 10-Bit Serial A/D Converter MCP3002T = 10-Bit Serial A/D Converter on tape and reel (SOIC and TSSOP packages only) Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. 2. 3. Your local Microchip sales office The Microchip Corporate Literature Center U.S. FAX: (480) 786-7277 The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products. 2000 Microchip Technology Inc. Preliminary DS21294A-page 17 MCP3002 NOTES: DS21294A-page 18 Preliminary 2000 Microchip Technology Inc. MCP3002 NOTES: 2000 Microchip Technology Inc. Preliminary DS21294A-page 19 WORLDWIDE SALES AND SERVICE AMERICAS Corporate Office Microchip Technology Inc. 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-786-7200 Fax: 480-786-7277 Technical Support: 480-786-7627 Web Address: http://www.microchip.com AMERICAS (continued) Toronto Microchip Technology Inc. 5925 Airport Road, Suite 200 Mississauga, Ontario L4V 1W1, Canada Tel: 905-405-6279 Fax: 905-405-6253 ASIA/PACIFIC (continued) Singapore Microchip Technology Singapore Pte Ltd. 200 Middle Road #07-02 Prime Centre Singapore 188980 Tel: 65-334-8870 Fax: 65-334-8850 ASIA/PACIFIC Beijing Microchip Technology, Beijing Unit 915, 6 Chaoyangmen Bei Dajie Dong Erhuan Road, Dongcheng District New China Hong Kong Manhattan Building Beijing 100027 PRC Tel: 86-10-85282100 Fax: 86-10-85282104 Taiwan Microchip Technology Taiwan 10F-1C 207 Tung Hua North Road Taipei, Taiwan Tel: 886-2-2717-7175 Fax: 886-2-2545-0139 Atlanta Microchip Technology Inc. 500 Sugar Mill Road, Suite 200B Atlanta, GA 30350 Tel: 770-640-0034 Fax: 770-640-0307 Boston Microchip Technology Inc. 5 Mount Royal Avenue Marlborough, MA 01752 Tel: 508-480-9990 Fax: 508-480-8575 EUROPE Denmark Microchip Technology Denmark ApS Regus Business Centre Lautrup hoj 1-3 Ballerup DK-2750 Denmark Tel: 45 4420 9895 Fax: 45 4420 9910 Hong Kong Microchip Asia Pacific Unit 2101, Tower 2 Metroplaza 223 Hing Fong Road Kwai Fong, N.T., Hong Kong Tel: 852-2-401-1200 Fax: 852-2-401-3431 Chicago Microchip Technology Inc. 333 Pierce Road, Suite 180 Itasca, IL 60143 Tel: 630-285-0071 Fax: 630-285-0075 France Arizona Microchip Technology SARL Parc d'Activite du Moulin de Massy 43 Rue du Saule Trapu Batiment A - ler Etage 91300 Massy, France Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 India Microchip Technology Inc. India Liaison Office No. 6, Legacy, Convent Road Bangalore 560 025, India Tel: 91-80-229-0061 Fax: 91-80-229-0062 Dallas Microchip Technology Inc. 4570 Westgrove Drive, Suite 160 Addison, TX 75248 Tel: 972-818-7423 Fax: 972-818-2924 Japan Microchip Technology Intl. Inc. Benex S-1 6F 3-18-20, Shinyokohama Kohoku-Ku, Yokohama-shi Kanagawa 222-0033 Japan Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Germany Arizona Microchip Technology GmbH Gustav-Heinemann-Ring 125 D-81739 Munchen, Germany Tel: 49-89-627-144 0 Fax: 49-89-627-144-44 Dayton Microchip Technology Inc. Two Prestige Place, Suite 150 Miamisburg, OH 45342 Tel: 937-291-1654 Fax: 937-291-9175 Italy Arizona Microchip Technology SRL Centro Direzionale Colleoni Palazzo Taurus 1 V. Le Colleoni 1 20041 Agrate Brianza Milan, Italy Tel: 39-039-65791-1 Fax: 39-039-6899883 Detroit Microchip Technology Inc. Tri-Atria Office Building 32255 Northwestern Highway, Suite 190 Farmington Hills, MI 48334 Tel: 248-538-2250 Fax: 248-538-2260 Korea Microchip Technology Korea 168-1, Youngbo Bldg. 3 Floor Samsung-Dong, Kangnam-Ku Seoul, Korea Tel: 82-2-554-7200 Fax: 82-2-558-5934 Los Angeles Microchip Technology Inc. 18201 Von Karman, Suite 1090 Irvine, CA 92612 Tel: 949-263-1888 Fax: 949-263-1338 United Kingdom Arizona Microchip Technology Ltd. 505 Eskdale Road Winnersh Triangle Wokingham Berkshire, England RG41 5TU Tel: 44 118 921 5858 Fax: 44-118 921-5835 01/21/00 Shanghai Microchip Technology Unit B701, Far East International Plaza, No. 317, Xianxia Road Shanghai, 200051 P.R.C Tel: 86-21-6275-5700 Fax: 86-21-6275-5060 New York Microchip Technology Inc. 150 Motor Parkway, Suite 202 Hauppauge, NY 11788 Tel: 631-273-5305 Fax: 631-273-5335 San Jose Microchip Technology Inc. 2107 North First Street, Suite 590 San Jose, CA 95131 Tel: 408-436-7950 Fax: 408-436-7955 Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999. The Company's quality system processes and procedures are QS-9000 compliant for its PICmicro(R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs and microperipheral products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001 certified. All rights reserved. (c) 2000 Microchip Technology Incorporated. Printed in the USA. 3/00 Printed on recycled paper. Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, except as maybe explicitly expressed herein, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies. 2000 Microchip Technology Inc. |
Price & Availability of MCP3002
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |